`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:27:50 07/08/2015 
// Design Name: 
// Module Name:    LatchMEMWB 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module LatchMEMWB(
	input [31:0] salidaE4In,
	//input PCSrcIn,
	//input [31:0] salidaAdder1In,
	input [4:0] salidaMux1In,
	input RegWrite1In,
	input MemToRegIn,
	input [31:0] ALUdataIn,
	input clk,
	output reg [31:0] salidaE4Out,
	//output reg PCSrcOut,
	//output reg [31:0] salidaAdder1Out,
	output reg [4:0] salidaMux1Out,
	output reg RegWrite1Out,
	output reg MemToRegOut,
	output reg [31:0] ALUdataOut
    );


always@(negedge clk) begin
	salidaE4Out = salidaE4In;
	//PCSrcOut = PCSrcIn;
	//salidaAdder1Out = salidaAdder1In;
	salidaMux1Out = salidaMux1In;
	RegWrite1Out = RegWrite1In;
	MemToRegOut = MemToRegIn;
	ALUdataOut = ALUdataIn;
end

endmodule
